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14-bit, 40 msps/65 msps a/d converter ad9244 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 14-bit, 40 msps/65 msps adc low power 550 mw at 65 msps 300 mw at 40 msps on-chip reference and sample-and-hold 750 mhz analog input bandwidth snr > 73 dbc to nyquist @ 65 msps sfdr > 86 dbc to nyquist @ 65 msps differential nonlinearity error = 0.7 lsb guaranteed no missing codes over full temperature range 1 v to 2 v p-p differential full-scale analog input range single 5 v analog supply, 3.3 v/5 v driver supply out-of-range indicator straight binary or twos complement output data clock duty cycle stabilizer output-enable function 48-lead lqfp package functional block diagram clk? vin+ vin? dcs agnd dgnd vref sense oeb d13 to d0 otr dfs a vdd drvdd ad9244 sha timing reference output register ref gnd vr cml clk+ 10-stage pipeline adc reft refb 14 14 02404-001 figure 1. applications communication subsystems (microcell, picocell) medical and high-end imaging equipment test and measurement equipment general description the ad9244 is a monolithic, single 5 v supply, 14-bit, 40 msps/65 msps adc with an on-chip, high performance sample-and-hold amplifier (sha) and voltage reference. the ad9244 uses a multistage differential pipelined architec- ture with output error correction logic to provide 14-bit accuracy at 40 msps/65 msps data rates, and guarantees no missing codes over the full operating temperature range. the ad9244 has an on-board, programmable voltage reference. an external reference can also be used to suit the dc accuracy and temperature drift requirements of the application. a differential or single-ended clock input controls all internal conversion cycles. the digital output data can be presented in straight binary or in twos complement format. an out-of-range (otr) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. fabricated on an advanced cmos process, the ad9244 is available in a 48-lead lqfp and is specified for operation over the industrial temperature range (C40c to +85c). product highlights 1. low power the ad9244, at 550 mw, consumes a fraction of the power of currently available adcs in existing high speed solutions. 2. if sampling the ad9244 delivers outstanding performance at input frequencies beyond the first nyquist zone. sampling at 65 msps with an input frequency of 100 mhz, the ad9244 delivers 71 db snr and 86 db sfdr. 3. pin compatibility the ad9244 offers a seamless migration from the 12-bit, 65 msps ad9226 . 4. on-board sample-and-hold (sha) the versatile sha input can be configured for either single-ended or differential inputs. 5. out-of-range (otr) indicator the otr output bit indicates when the input signal is beyond the ad9244s input range. 6. single supply the ad9244 uses a single 5 v power supply, simplifying system power supply design. it also features a separate digital output driver supply to accommodate 3.3 v and 5 v logic families.
ad9244 rev. c | page 2 of 36 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 absolute maximum ratings ............................................................ 7 explanation of test levels ........................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 ter mi nolo g y .......................................................................................9 typical application circuits ......................................................... 11 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 17 analog input and reference overview ................................... 17 analog input operation ............................................................ 18 reference operation .................................................................. 20 digital inputs and outputs ....................................................... 21 evaluation board ............................................................................ 26 analog input configuration ..................................................... 26 reference configuration ........................................................... 26 clock configuration .................................................................. 26 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 12/05rev. b to rev. c updated format..................................................................universal changes to figure 45...................................................................... 19 added single-ended input configuration section.................... 19 added reference decoupling section ......................................... 25 changes to figure 65...................................................................... 28 changes to figure 66...................................................................... 29 changes to figure 67...................................................................... 30 added table 15 ............................................................................... 34 2/05rev. a to rev. b updated format..................................................................universal changes to table 1.............................................................................3 changes to table 2.............................................................................4 reformatted table 5 ..........................................................................7 changes to table 6.............................................................................8 changes to figure 12...................................................................... 12 changed captions on figure 18 and figure 21 .......................... 13 changes to figure 35, figure 38, figure 39................................. 16 changes to table 9.......................................................................... 18 changes to table 13 ....................................................................... 26 changes to ordering guide .......................................................... 36 6/03rev. 0 to rev. a changes to ac specifications ..........................................................3 updated ordering guide .................................................................6 updated outline dimensions....................................................... 33 6/02revision 0: initial version
ad9244 rev. c | page 3 of 36 specifications dc specifications avdd = 5 v, drvdd = 3 v, f sample = 65 msps (C65) or 40 msps (C40), differential clock inputs, vref = 2 v, external reference, differential analog inputs, unless otherwise noted. table 1. test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit resolution full vi 14 14 bits dc accuracy no missing codes full vi guaranteed guaranteed bits offset error full vi 0.3 1.4 0.3 1.4 % fsr gain error 1 full vi 0.6 2.0 0.6 2.0 % fsr differential nonlinearity (dnl) 2 full vi 1.0 1.0 lsb 25c v 0.7 0.6 lsb integral nonlinearity (inl) 2 full v 1.4 1.3 lsb full vi ?4 +4 ?4 +4 lsb temperature drift offset error full v 2.0 2.0 ppm/c gain error (ext vref) 1 full v 2.3 2.3 ppm/c gain error (int vref) 3 full v 25 25 ppm/c internal voltage reference output voltage error (2 vref) full vi 29 29 mv load regulation @ 1 ma full v 0.5 0.5 mv output voltage error (1 vref) full iv 15 15 mv load regulation @ 0.5 ma full v 0.25 0.25 mv input resistance full v 5 5 k input referred noise vref = 2 v 25c v 0.8 0.8 lsb rms vref = 1 v 25c v 1.5 1.5 lsb rms analog input input voltage range (differential) vref = 2 v full v 2 2 v p-p vref = 1 v full v 1 1 v p-p common-mode voltage full v 0.5 4 0.5 4 v input capacitance 4 25c v 10 10 pf input bias current 5 25c v 500 500 a analog bandwidth (full power) 25c v 750 750 mhz power supplies supply voltages avdd full iv 4.75 5 5.25 4.75 5 5.25 v drvdd full iv 2.7 5.25 2.7 5.25 v supply current iavdd full v 109 64 ma idrvdd full v 12 8 ma psrr full v 0.05 0.05 % fsr power consumption dc input 6 full v 550 300 mw sine wave input full vi 590 640 345 370 mw 1 gain error is based on the adc only (with a fixed 2.0 v external reference). 2 measured at maximum clock rate, f in = 2.4 mhz, full-scale sine wave, with approx imately 5 pf loading on each output bit. 3 includes internal vo ltage reference error. 4 input capacitance refers to the effectiv e capacitance between one differential input pin and agnd. refer to figure 7 for the e quivalent analog input structure. 5 input bias current is due to the input looking li ke a resistor that is dependent on the clock rate. 6 measured with dc input at maximum clock rate.
ad9244 rev. c | page 4 of 36 ac specifications avdd = 5 v, drvdd = 3 v, f sample = 65 msps (C65) or 40 msps (C40), differential clock inputs, vref = 2 v, external reference, a in = C0.5 dbfs, differential analog inputs, unless otherwise noted. table 2. test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit snr 1 f in = 2.4 mhz full vi 72.4 73.4 dbc 25c i 74.8 75.3 dbc f in = 15.5 mhz (C1 dbfs) full iv 72.0 dbc 25c v 73.7 dbc f in = 20 mhz full vi 72.1 dbc 25c i 74.7 dbc f in = 32.5 mhz full iv 70.8 dbc 25c i 73.0 dbc f in = 70 mhz full iv 69.9 dbc 25c v 72.2 dbc f in = 100 mhz 25c v 71.2 72.8 dbc f in = 200 mhz 25c v 67.2 68.3 dbc sinad 1 f in = 2.4 mhz full vi 72.2 73.2 dbc 25c i 74.7 75.1 dbc f in = 20 mhz full vi 72 dbc 25c i 74.4 dbc f in = 32.5 mhz full iv 70.6 dbc 25c i 72.6 dbc f in = 70 mhz full iv 69.7 dbc 25c v 71.9 dbc f in = 100 mhz 25c v 71 72.4 dbc f in = 200 mhz 25c v 59.8 56.3 dbc enob f in = 2.4 mhz full vi 11.7 11.9 bits 25c i 12.1 12.2 bits f in = 20 mhz full vi 11.7 bits 25c i 12.1 bits f in = 32.5 mhz full iv 11.4 bits 25c i 11.8 bits f in = 70 mhz full iv 11.3 bits 25c v 11.7 bits f in = 100 mhz 25c v 11.5 11.7 bits f in = 200 mhz 25c v 9.6 9.1 bits thd 1 f in = 2.4 mhz full vi ?78.4 ?80.7 dbc 25c i ?90.0 ?89.7 dbc f in = 20 mhz full vi ?80.4 dbc 25c i ?89.4 dbc f in = 32.5 mhz full iv ?79.2 dbc 25c i ?84.6 dbc f in = 70 mhz full iv ?78.7 dbc 25c v ?84.1 dbc f in = 100 mhz 25c v ?83.0 ?83.2 dbc f in = 200 mhz 25c v ?60.7 ?56.6 dbc
ad9244 rev. c | page 5 of 36 test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit worst harmonic (second or third) 1 f in = 2.4 mhz 25c v ?94.5 ?93.7 dbc f in = 20 mhz 25c v ?92.8 dbc f in = 32.5 mhz 25c v ?86.5 dbc f in = 70 mhz 25c v ?86.1 dbc f in = 100 mhz 25c v ?86.2 ?84.5 dbc f in = 200 mhz 25c v ?60.7 ?56.6 dbc sfdr 1 f in = 2.4 mhz full vi 78.6 82.5 dbc 25c i 94.5 93.7 dbc f in = 15.5 mhz (C1 dbfs) full iv 83 dbc 25c v 90 dbc f in = 20 mhz full iv 81.4 dbc 25c i 91.8 dbc f in = 32.5 mhz full iv 80.0 dbc 25c i 86.4 dbc f in = 70 mhz full iv 79.5 dbc 25c v 86.1 dbc f in = 100 mhz 25c v 86.2 84.5 dbc f in = 200 mhz 25c v 60.7 56.6 dbc 1 ac specifications can be reported in dbc (degrades as signal levels are lowered) or in dbfs (always related back to converter full scale). digital specifications avdd = 5 v, drvdd = 3 v, vref = 2 v, external reference, unless otherwise noted. table 3. test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit digital inputs logic 1 voltage (oeb, drvdd = 3 v) full iv 2 2 v logic 1 voltage (oeb, drvdd = 5 v) full iv 3.5 3.5 v logic 0 voltage (oeb) full iv 0.8 0.8 v logic 1 voltage (dfs, dcs) full iv 3.5 3.5 v logic 0 voltage (dfs, dcs) full iv 0.8 0.8 v input current full iv 10 10 a input capacitance full v 5 5 pf clock input parameters differential input voltage full iv 0.4 0.4 v p-p clk? voltage 1 full iv 0.25 0.25 v internal clock common-mode full v 1.6 1.6 v single-ended input voltage logic 1 voltage full iv 2 2 v logic 0 voltage full iv 0.8 0.8 v input capacitance full v 5 5 pf input resistance full v 100 100 k digital outputs (drvdd = 5 v) logic 1 voltage (i oh = 50 a) full iv 4.5 4.5 v logic 0 voltage (i ol = 50 a) full iv 0.1 0.1 v logic 1 voltage (i oh = 0.5 ma) full iv 2.4 2.4 v logic 0 voltage (i ol = 1.6 ma) full iv 0.4 0.4 v
ad9244 rev. c | page 6 of 36 test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit digital outputs (drvdd = 3 v) 2 logic 1 voltage (i oh = 50 a) full iv 2.95 2.95 v logic 0 voltage (i ol = 50 a) full iv 0.05 0.05 v logic 1 voltage (i oh = 0.5 ma) full iv 2.8 2.8 v logic 0 voltage (i ol = 1.6 ma) full iv 0.4 0.4 v 1 see the clock overview section for more details. 2 output voltage levels measured with 5 pf load on each output. switching specifications avdd = 5 v, drvdd = 3 v, unless otherwise noted. table 4. test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit clock input parameters maximum conversion rate full vi 65 40 mhz minimum conversion rate full v 500 500 khz clock period 1 full v 15.4 25 ns clock pulse width high 2 full v 4 4 ns clock pulse width low 2 full v 4 4 ns clock pulse width high 3 full v 6.9 11.3 ns clock pulse width low 3 full v 6.9 11.3 ns data output parameters output delay (t pd ) 4 full v 3.5 7 3.5 7 ns pipeline delay (latency) full v 8 8 clock cycles aperture delay (t a ) full v 1.5 1.5 ns aperture uncertainty (jitter) full v 0.3 0.3 ps rms output enable delay full v 15 15 ns out-of-range recovery time full v 2 1 clock cycles 1 the clock period can be extended to 2 s with no degradation in specified performance at 25c. 2 with duty cycle stabilizer enabled. 3 with duty cycle stabilizer disabled. 4 measured from clock 50% transition to data 50% transition with 5 pf load on each output. n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 analog input clock data out t pd t a n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 02404-002 figure 2. input timing
ad9244 rev. c | page 7 of 36 absolute maximum ratings table 5. parameter with respect to rating electrical avdd agnd C0.3 v to +6.5 v drvdd dgnd ?0.3 v to +6.5 v agnd dgnd C0.3 v to +0.3 v avdd drvdd C6.5 v to +6.5 v refgnd agnd C0.3 v to +0.3 v clk+, clkC, dcs agnd C0.3 v to avdd + 0.3 v dfs agnd C0.3 v to avdd + 0.3 v vin+, vinC agnd C0.3 v to avdd + 0.3 v vref agnd C0.3 v to avdd + 0.3 v sense agnd C0.3 v to avdd + 0.3 v refb, reft agnd C0.3 v to avdd + 0.3 v cml agnd C0.3 v to avdd + 0.3 v vr agnd C0.3 v to avdd + 0.3 v otr dgnd C0.3 v to drvdd + 0.3 v d0 to d13 dgnd C0.3 v to drvdd + 0.3 v oeb dgnd C0.3 v to drvdd + 0.3 v environmental 1 junction temperature 150c storage temperature ?65c to +150c operating temperature ?40c to +85c lead temperature (10 sec) 300c 1 typical thermal impedances; ja = 50.0c/w; jc = 17.0c/w. these measurements were taken on a 4-layer board in still air, in accordance with eia/jesd51-7. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. explanation of test levels table 6. test level description i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad9244 rev. c | page 8 of 36 pin configuration and fu nction descriptions 48 vr 47 vin? 46 vin+ 45 cml 44 nic 43 dcs 42 reft 41 reft 40 refb 39 refb 38 refgnd 37 vref 35 dfs 34 avdd 33 agnd 30 dgnd 31 avdd 32 agnd 36 sense 29 drvdd 28 otr 27 d13 (msb) 25 d11 26 d12 2 agnd 3 avdd 4 avdd 7 clk+ 6 clk? 5 agnd 1 agnd 8 nic 9 oeb 10 d0 (lsb) 12 d2 11 d1 13 d3 14 dgnd 15 drvdd 16 d4 17 d5 18 d6 19 d7 20 d8 21 d9 22 dgnd 23 drvdd 24 d10 pin 1 ad9244 top view (not to scale) 02404-003 figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic description 1, 2, 5, 32, 33 agnd analog ground. 3, 4, 31, 34 avdd analog supply voltage. 6, 7 clkC, clk+ differential clock inputs. 8, 44 nic no internal connection. 9 oeb digital output enable (active low). 10 d0 (lsb) least significant bit, digital output. 11 to 13, 16 to 21, 24 to 26 d1 to d3, d4 to d9, d10 to d12 digital outputs. 14, 22, 30 dgnd digital ground. 15, 23, 29 drvdd digital supply voltage. 27 d13 (msb) most significant bit, digital output. 28 otr out-of-range indicator (logic 1 indicates otr). 35 dfs data format select. connect to agnd for straight binary, avdd for twos complement. 36 sense internal reference control. 37 vref internal reference. 38 refgnd reference ground. 39 to 42 refb, reft internal reference decoupling. 43 dcs 50% duty cycle stabilizer. connect to avdd to activate 50% duty cycle stabilizer, agnd for external control of both clock edges. 45 cml common-mode reference (0.5 avdd). 46, 47 vin+, vinC differential analog inputs. 48 vr internal bias decoupling.
ad9244 rev. c | page 9 of 36 terminology analog bandwidth (full power bandwidth) the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input voltage range the peak-to-peak differential voltage must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. peak-to-peak differential is computed by rotating the input phase 180 and taking the peak measurement again. the difference is then found between the two peak measurements. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges. dual-tone sfdr 1 the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. effective number of bits (enob) the enob for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad by n = ( sinad ? 1.76)/6.02 gain error the first code transition should occur at an analog value ? lsb above negative full scale. the last code transition should occur at an analog value 1? lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. common-mode rejection ratio (cmrr) common-mode (cm) signals appearing on vin+ and vinC are ideally rejected by the differential front end of the adc. with a full-scale cm signal driving both vin+ and vinC, cmrr is the ratio of the amplitude of the full-scale input cm signal to the amplitude of signal that is not rejected, expressed in dbfs. 1 if sampling due to the effects of aliasing, an adc is not necessarily limited to nyquist sampling. higher sampled frequencies are aliased down into the first nyquist zone (dc ? f clock /2) on the output of the adc. care must be taken that the bandwidth of the sam- pled signal does not overlap nyquist zones and alias onto itself. nyquist sampling performance is limited by the bandwidth of the input sha and clock jitter (noise caused by jitter increases as the input frequency increases). integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. nyquist sampling when the frequency components of the analog input are below the nyquist frequency (f clock /2). out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. power supply rejection ratio (psrr) the change in full scale from the value with the supply at its minimum limit to the value with the supply at its maximum limit. signal-to-noise-and-distortion (sinad) 1 t t he ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the nyquist frequency, including harmonics, but excluding dc. signal-to-noise ratio (snr) 1 the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc.
ad9244 rev. c | page 10 of 36 spurious-free dynamic range (sfdr) 1 the difference in db between the rms amplitude of the input signal and the peak spurious signal. temp er atu re d r i f t the temperature drift for offset error and gain error specifies the maximum change from initial (25c) value to the value at t min or t max . total harmonic distortion (thd) 1 the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. offset error the major carry transition should occur for an analog value ? lsb below vin+ = vin?. offset error is defined as the deviation of the actual transition from that point. 1 ac specifications can be reported in dbc (degrades as signal levels are lowered) or in dbfs (always related back to converter full scale).
ad9244 rev. c | page 11 of 36 typical application circuits drvdd drvdd dgnd 02404-004 figure 4. d0 to d13, otr dgnd drvdd 200 02404-005 figure 5. three-state (oeb) 200 agnd avdd clk buffer 02404-006 figure 6. clk+, clk? agnd avdd 02404-007 figure 7. vin+, vin? 200 agnd avdd 02404-008 figure 8. dfs, dcs, sense agnd avdd 02404-009 figure 9. vref, reft, refb, vr, cml
ad9244 rev. c | page 12 of 36 typical performance characteristics avdd = 5.0 v, drvdd = 3.0 v, f sample = 65 msps with clk duty cycle stabilizer enabled, t a = 25c, differential analog input, common- mode voltage (v cm ) = 2.5 v, input amplitude (a in ) = ?0.5 dbfs, vref = 2.0 v external, fft length = 8k, unless otherwise noted. 02404-010 frequency (mhz) 32.5 01 0 5 15202530 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?120 ?100 snr = 74.8dbc sfdr = 93.6dbc figure 10. single-tone fft, f in = 5 mhz 02404-011 frequency (mhz) 32.5 0 10.0 5.0 15.0 20.0 25.0 30.0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 74.0dbc sfdr = 87.0dbc figure 11. single-tone fft, f in = 31 mhz 02404-012 frequency (mhz) 0 5 10 15 20 25 30 amplitude (dbfs) 0 ?20 ?40 ?60 ?100 ?80 ?120 snr = 66.5dbc sfdr = 74.0dbc figure 12. single-tone fft, f in = 190 mhz, f sample = 61.44 msps 02404-013 a in (dbfs) 0 ?30 ?25 ?20 ?15 ?10 ?5 dbfs and dbc 100 80 90 70 60 50 40 sfdr (dbfs) snr (dbfs) snr (dbc) sfdr = 90dbc reference line sfdr (dbc) figure 13. single-tone snr/sfdr vs. a in , f in = 5 mhz 02404-014 a in (dbfs) 0 30 ?25 ?20 ?15 ?10 ?5 dbfs and dbc 100 90 80 70 60 50 40 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr = 90dbc reference line figure 14. single-tone snr/sfdr vs. a in , f in = 31 mhz 02404-015 a in (dbfs) 0 ?30 ?25 ?20 ?15 ?10 ?5 dbfs and dbc 100 90 80 70 60 50 40 snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) sfdr = 90dbc reference line figure 15. single-tone snr/sfdr vs. a in , f in = 190 mhz, f sample = 61.44 msps
ad9244 rev. c | page 13 of 36 02404-016 enob (bits) 10.5 12.2 11.9 11.5 11.2 10.8 input frequency (mhz) 140 0 20406080100120 sinad (dbc) 75 73 71 69 67 65 2v span 1v span figure 16. sinad/enob vs. input frequency 02404-017 input frequency (mhz) 140 0 20 40 60 80 100 120 thd (dbc) ?100 ?95 ?90 ?85 ?80 ?75 2v span 1v span figure 17. thd vs. input frequency 02404-018 input frequency (mhz) 140 0 20 40 60 80 100 120 snr (dbc) 77 75 73 71 69 67 +25c +85c ?40c figure 18. snr vs. temperature and input frequency, dcs disabled 02404-019 input frequency (mhz) 140 0 20 40 60 80 100 120 snr (dbc) 75 73 71 69 67 65 2v span 1v span figure 19. snr vs. input frequency 02404-020 input frequency (mhz) 140 0 20 40 60 80 100 120 sfdr (dbc) 100 95 90 85 80 75 2v span 1v span figure 20. sfdr vs. input frequency 02404-021 input frequency (mhz) 140 0 20 40 60 80 100 120 thd (dbc) ?92 ?88 ?90 ?84 ?86 ?80 ?82 ?76 ?78 ?74 ?40c +85c +25c figure 21. thd vs. temperature and input frequency, dcs disabled
ad9244 rev. c | page 14 of 36 02404-022 input frequency (mhz) 140 0 20 40 60 80 100 120 harmonics (dbc) ?100 ?95 ?90 ?85 ?80 ?75 fourth harmonic second harmonic third harmonic figure 22. harmonics vs. input frequency 02404-023 enob (bits) 11.34 12.33 12.17 12.00 11.67 11.50 11.83 sampe rate (msps) 100 0 20406080 sinad (dbc) 76 75 74 73 72 71 70 f in = 20mhz f in = 10mhz f in = 2mhz figure 23. sinad/enob vs. sample rate 02404-024 codes (14-bit) 16384 0 4096 8192 12288 inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 figure 24. typical inl 02404-025 duty cycle (%) 70 30 35 40 45 50 55 60 65 snr/sfdr (dbc) 100 95 90 85 80 75 60 65 60 snr, dcs on sfdr, dcs on sfdr, dcs off snr, dcs off figure 25. snr/sfdr vs. duty cycle, f in = 2.5 mhz 02404-026 sample rate (msps) 100 0 20406080 sfdr (dbc) 100 96 92 88 84 80 f in = 2mhz f in = 10mhz f in = 20mhz figure 26. sfdr vs. sample rate 02404-027 codes (14-bit) 16384 0 4096 8192 12288 dnl (lsb) 1.0 0.8 0.6 0.4 0.2 ?0.4 ?0.2 0 ?0.6 ?0.8 ?1.0 figure 27. typical dnl
ad9244 rev. c | page 15 of 36 02404-028 frequency (mhz) 32.5 0 10.0 5.0 20.0 15.0 25.0 30.0 amplitude (dbfs) 0 ?20 ?60 ?40 ?80 ?100 ?120 snr = 67.5dbc sfdr = 93.2dbc figure 28. dual-tone fft with f in?1 = 44.2 mhz and f in?2 = 45.6 mhz (a in1 = a in2 = C6.5 dbfs) 02404-029 frequency (mhz) 32.5 0 10.0 5.0 25.0 20.0 15.0 3 0 . 0 amplitude (dbfs) 0 20 40 60 80 100 120 snr = 67.0dbc sfdr = 78.2dbc figure 29. dual-tone fft with f in?1 = 69.2 mhz and f in?2 = 70.6 mhz (a in1 = a in2 = C6.5 dbfs) 02404-030 frequency (mhz) 32.5 0 5.0 10.0 15.0 20.0 25.0 30.0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 65.0dbc sfdr = 69.1dbc figure 30. dual-tone fft with f in?1 = 139.2 mhz and f in?2 = 140.7 mhz (a in1 = a in2 = C6.5 dbfs) 02404-031 a in (dbfs) ?5 ?30 ?25 ?20 ?15 ?10 dbfs and dbc 100 90 80 70 60 50 40 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr = 90dbc reference line figure 31. dual-tone snr/sfdr vs. a in with f in?1 = 44.2 mhz and f in?2 = 45.6 mhz 02404-032 a in (dbfs) ?5 ?30 ?25 ?20 ?15 ?10 dbfs and dbc 100 90 80 70 60 50 40 snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) sfdr = 90dbc reference line figure 32. dual-tone snr/sfdr vs. a in with f in?1 = 69.2 mhz and= f in?2 = 70.6 mhz 02404-033 a in (dbfs) ?5 ?30 ?25 ?20 ?15 ?10 dbfs and dbc 100 90 80 70 60 50 40 sfdr (dbfs) snr (dbfs) snr (dbc) sfdr (dbc) sfdr = 90dbc reference line figure 33. dual-tone snr/sfdr vs. a in with f in?1 = 139.2 mhz and f in?2 = 140.7 mhz
ad9244 rev. c | page 16 of 36 02404-034 frequency (mhz) 32.5 05 25 20 15 10 30.0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 62.6dbc sfdr = 60.7dbc figure 34. dual-tone with f in?1 = 239.1 mhz and f in?2 = 240.7 mhz (a in?1 = a in?2 = C6.5 dbfs) 02404-035 frequency (mhz) 0 5 10 15 20 25 30 amplitude (dbfs) 0 ?20 ?10 ?40 ?30 ?60 ?50 ?100 ?110 ?90 ?80 ?70 ?120 snr = 71.3dbc thd = ?90.8dbc note: spur floor below 90dbfs @ 240mhz figure 35. driving adc inputs with transformer and balun, f in = 240 mhz, a in = C8.5 dbfs 02404-036 input frequency (mhz) 250 0 50 100 150 200 amplitude (dbfs) 105 100 95 90 85 80 75 70 65 figure 36. cmrr vs. input frequency (a in = 0 dbfs and cml = 2.5 v) 02404-037 a in (dbfs) ?5 ?30 ?25 ?20 ?15 ?10 dbfs and dbc 100 90 80 70 60 50 40 sfdr = 90dbc reference line snr (dbc) sfdr (dbfs) snr (dbfs) sfdr (dbc) figure 37. dual-tone snr/sfdr vs. a in with f in?1 = 239.1 mhz and f in?2 = 240.7 mhz 02404-038 a in (dbfs) 0 ?21 ?18 ?15 ?12 ?9 ?6 ?3 dbfs and dbc 100 85 90 95 80 75 70 65 60 55 50 snr (dbc) snr (dbfs) sfdr (dbc) sfdr (dbfs) sfdr = 90dbc reference line figure 38. driving adc inputs with transformer and balun snr/sfdr vs. a in , f in = 240 mhz 02404-039 a in (dbfs) 0 ?21 ?18 ?15 ?12 ?9 ?6 ?3 dbfs and dbc 95 90 85 80 75 70 65 60 55 snr (dbc) snr (dbfs) sfdr (dbc) sfdr (dbfs) sfdr = 90dbc reference line figure 39. driving adc inputs with transformer and balun snr/sfdr vs. a in , f in = 190 mhz
ad9244 rev. c | page 17 of 36 theory of operation the ad9244 is a high performance, single-supply 14-bit adc. in addition to high dynamic range nyquist sampling, it is designed for excellent if undersampling performance with an analog input as high as 240 mhz. the ad9244 uses a calibrated 10-stage pipeline architecture with a patented, wideband, input sample-and-hold amplifier (sha) implemented on a cost-effective cmos process. each stage of the pipeline, excluding the last, consists of a low resolu- tion flash adc along with a switched capacitor dac and interstage residue amplifier (mdac). the mdac amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each of the stages to faci litate digital correction of flash errors. the last stage simply consists of a flash adc. the pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. while the converter cap- tures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and appear at the output, as illustrated in figure 2 . this latency is not a concern in many applications. the digital output, together with the otr indicator, is latched into an output buffer to drive the output pins. the output drivers of the ad9244 can be configured to interface with 5 v or 3.3 v logic families. the ad9244 has a duty clock stabilizer (dcs) that generates its own internal falling edge to create an internal 50% duty cycle clock, independent of the externally applied duty cycle. control of straight binary or twos complement output format is accom- plished with the dfs pin. the adc samples the analog input on the rising edge of the clock. while the clock is low, the input sha is in sample mode. when the clock transitions to a high logic level, the sha goes into the hold mode. system disturbances just prior to or imme- diately after the rising edge of the clock and/or excessive clock jitter can cause the sha to acquire the wrong input value and should be minimized. analog input and reference overview the differential input span of the ad9244 is equal to the poten- tial at the vref pin. the vref potential can be obtained from the internal ad9244 reference or an external source. in differential applications, the center point of the input span is the common-mode level of the input signals. in single-ended applications, the center point is the dc potential applied to one input pin while the signal is applied to the opposite input pin. figure 40 to figure 42 show various system configurations. reft refb vref sense ad9244 vin+ vin? 33 20pf 2v 10 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 33 50v refgnd + + 2.5v 1.5v 2 .5v 1.5v 02404-040 figure 40. 2 v p-p differential in put, common-mode voltage = 2 v reft refb vref sense ad9244 vin+ vin? 33 20pf 2v 10 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 33 refgnd + + 3.0v 2.0v 02404-041 figure 41. 2 v p-p single-ended in put, common-mode voltage = 2 v reft refb vref sense ad9244 vin+ vin? 33 20pf 0.1pf 2v 2.5v 10 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 33 50 refgnd + + 3.0v 2.0v 3 .0v 2 .0v 02404-042 figure 42. 2 v p-p differential inpu t, common-mode voltage = 2.5 v figure 43 is a simplified model of the ad9244 analog input, showing the relationship between the analog inputs, vin+, vinC, and the reference voltage, vref. note that this is only a symbolic model and that no actual negative voltages exist inside the ad9244. similar to the voltages applied to the top and bot- tom of the resistor ladder in a flash adc, the value vref/2 defines the minimum and maximum input voltages to the adc core. ad9244 +vref/2 ?vref/2 v in+ v in? v core + ? adc core 14 02404-043 figure 43. equivalent analog input of ad9244
ad9244 rev. c | page 18 of 36 a differential input structure allows the user to easily configure the inputs for either single-ended or differential operation. the adcs input structure allows the dc offset of the input signal to be varied independent of the input span of the converter. specifically, the input to the adc core can be defined as the difference of the voltages applied at the vin+ and vinC input pins. therefore, the equation v core = (vin+) C (vin?) (1) defines the output of the differential input stage and provides the input to the adc core. the voltage, v core , must satisfy the condition ?vref /2 < v core < vref /2 (2) where vref is the voltage at the v ref pin. in addition to the limitations placed on the input voltages vin+ and vinC by equation 1 and equation 2, boundaries on the inputs also exist based on the power supply voltages according to the conditions agnd ? 0.3 v < vin+ < avdd + 0.3 v (3) agnd ? 0.3 v < vin? < avdd + 0.3 v (4) where: agnd is nominally 0 v. avdd is nomi na l ly 5 v. the range of valid inputs for vin+ and vin? is any combination that satisfies equation 2, equation 3, and equation 4. for additional information showing the relationship between vin+, vinC, vref, and the analog input range of the ad9244, see tabl e 8 and table 9 . analog input operation figure 44 shows the equivalent analog input of the ad9244, which consists of a 750 mhz differential sha. the differential input structure of the sha is flexible, allowing the device to be configured for either a differential or single-ended input. the analog inputs vin+ and vinC are interchangeable, with the exception that reversing the inputs to the vin+ and vinC pins results in a data inversion (complementing the output word). s vin+ vin? c pin, par s h c s c s c h c pin, par s s c h 02404-044 figure 44. analog input of ad9244 sha table 8. analog input configuration summary input input input range (v) input cm connection coupling span (v) vin+ 1 vin? 1 voltage (v) comments single-ended dc or ac 1.0 0.5 to 1.5 1.0 1. 0 best for stepped input response applications. 2.0 1 to 3 2.0 2.0 optimum noise performance for single-ended mode often requires low distortion op amp with vcc > 5 v due to its headroom issues. differential dc or ac 1.0 2.25 to 2.75 2.75 to 2.25 2.5 optimum full-scale thd and sfdr performance well beyond the adcs nyquist frequency. 2.0 2.0 to 3.0 3.0 to 2.0 2.5 optimum noise performance for differential mode. preferred mode for applications. 1 vin+ and vin ? can be interchanged if data inversion is required. table 9. reference configuration summary reference operating mode connect to resulting vref (v) input span (vin+ ? vin?) (v p-p) internal sense vref 1 1 internal sense agnd 2 2 internal r1 vref and sense 1 vref 2.0 1 span 2 r2 sense and refgnd vref = (1 + r1/r2) (span = vref) external sense avdd 1 vref 2.0 span = external ref vref external ref
ad9244 rev. c | page 19 of 36 the optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (that is, 2 v input span) and matched input impedance for vin+ and vinC. only a slight degradation in dc linearity performance exists between the 2 v and 1 v input spans; however, the snr is lower in the 1 v input span. when the adc is driven by an op amp and a capacitive load is switched onto the output of the op amp, the output momentar- ily drops due to its effective output impedance. as the output recovers, ringing can occur. to remedy the situation, a series resistor, r s , can be inserted between the op amp and the sha input, as shown in figure 45 . a shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the sampling capacitor, c s , further reducing current transients seen at the op amps output. vref sense ad9244 vin+ vin? r s 33 c s 20pf 10 f 0.1 f r s 33 5 refcom + 0.1 f v cc v ee 02404-045 figure 45. resistors isolating sha input from op amp the optimum size of this resistor is dependent on several factors, including the adc sampling rate, the selected op amp, and the particular application. in most applications, a 30 to 100 resistor is sufficient. for noise-sensitive applications, the very high bandwidth of the ad9244 can be detrimental, and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the adcs input by forming a low-pass filter. the source impedance driving vin+ and vin? should be matched. failure to provide matching can result in degradation of the snr, thd, and sfdr performance. single-ended input configuration a single-ended input can provide adequate performance in cost-sensitive applications. in this configuration, there is degradation in distortion performance due to large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. the internal reference can be used to drive the inputs. figure 45 shows an example of vref driving vin?. in this operating mode, a 5 resistor and a 0.1 f capacitor must be connected between vref and vin?, as shown in figure 45 , to limit the reference noise sampled by the analog input. differentially driving the analog inputs the ad9244 has a very flexible input structure, allowing it to interface with single-ended or differential inputs. the optimum mode of operation, analog input range, and associ- ated interface circuitry is determined by the particular applications performance requirements as well as power supply options. differential operation requires that vin+ and vin? be simultaneously driven with two equal signals that are 180out of phase with each other. differential modes of operation (ac-coupled or dc-coupled input) provide the best sfdr performance over a wide frequency range. they should be considered for the most demanding spectral- based applications; that is, direct if conversion to digital. because not all applications have a signal precondition for differential operation, there is often a need to perform a single- ended-to-differential conversion. in systems that do not require dc coupling, an rf transformer with a center tap is the best method for generating differential input signals for the ad9244. this provides the benefit of operating the adc in the differen- tial mode without contributing additional noise or distortion. an rf transformer also has the added benefit of providing electrical isolation between the signal source and the adc. the differential input characterization was performed using the configuration in figure 46 . the circuit uses a mini-circuits? rf transformer, model t1-1t, which has an impedance ratio of 1:1. this circuit assumes that the signal source has a 50 source impedance. the secondary center tap of the transformer allows a dc common-mode voltage to be added to the differential input signal. in figure 46 , the center tap is connected to a resistor divider providing a half supply voltage. it could also be connected to the cml pin of the ad9244. for if sampling applications (70 mhz < f in < 200 mhz), it is recommended that the 20 pf differential capacitor between vin+ and vin? be reduced or removed. reft refb ad9244 vin+ vin? r s 33 20pf 0.1 f 0.1 f 0.1 f 10 f r s 33 50 + 1k 1k 0.1 f avdd mini-circuits t1?1t 02404-046 figure 46. transformer-coupled input
ad9244 rev. c | page 20 of 36 the circuit in figure 47 shows a method for applying a differential, direct-coupled signal to the ad9244. an ad8138 amplifier is used to derive a differential signal from a single-ended signal. reft refb ad9244 vin+ avdd vin? 33 20pf 0.1 f 0.1 f 0.1 f 10 f 33 + 499 499 499 ad8138 499 475 50 1k 1k 1v p-p 0v 10 f 10 f 10 f 0.1 f 0.1 f 5v 02404-047 + + figure 47. direct-coupled drive circuit with ad8138 differential op amp reference operation the ad9244 contains a band gap reference that provides a pin- strappable option to generate either a 1 v or 2 v output. with the addition of two external resistors, the user can generate reference voltages between 1 v and 2 v. another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance, as described later in this section. figure 48 shows a simplified model of the internal voltage reference of the ad9244. a reference amplifier buffers a 1 v fixed reference. the output from the reference amplifier, a1, appears on the vref pin. as stated earlier, the voltage on the vref pin determines the full-scale differential input span of the adc. to adc reft refb vref sense refgnd ad9244 2.5v 1v logic disable a1 r r a1 02404-048 a2 figure 48. equivalent reference circuit the voltage appearing at the vref pin and the state of the internal reference amplifier, a1, are determined by the voltage present at the sense pin. the logic circuitry contains compara- tors that monitor the voltage at the sense pin. the various reference modes are summarized in table 9 and are described in the next few sections. the actual reference voltages used by the internal circuitry of the ad9244 appear on the reft and refb pins. the voltages on these pins are symmetrical about midsupply or cml. for proper operation, it is necessary to add a capacitor network to decouple these pins. figure 49 shows the recommended decoupling network. the turn-on time of the reference voltage appearing between reft and refb is approximately 10 ms and should be taken into consideration in any power-down mode of operation. the vref pin should be bypassed to the refgnd pin with a 10 f tantalum capacitor in parallel with a low inductance 0.1 f ceramic capacitor. 10 f 0.1 f 0.1 f 0.1 f 0.1 f 1 10 f vref reft refb ad9244 1 locate as close as possible to reft/refb pins. refgnd + + 02404-049 figure 49. reference decoupling pin-programmable reference by shorting the vref pin directly to the sense pin, the inter- nal reference amplifier is placed in a unity gain mode, and the resulting vref output is 1 v. by shorting the sense pin directly to the refgnd pin, the internal reference amplifier is configured for a gain of 2, and the resulting vref output is 2 v. resistor-programmable reference figure 50 shows an example of how to generate a reference voltage other than 1.0 v or 2.0 v with the addition of two external resistors. use the equation vref = 1 v (1 + r1 / r2 ) (5) to determine the appropriate values for r1 and r2. these resistors should be in the 2 k to 10 k range. for the example shown, r1 equals 2.5 k and r2 equals 5 k. from the previous equation, the resulting reference voltage on the vref pin is 1.5 v. this sets the differential input span to 1.5 v p-p. the midscale voltage can also be set to vref by connecting vin? to vref. r1 2.5k r2 5k vref sense ad9244 vin+ vin? 33 20pf 1.5v 33 refgnd 3.25v 1.75v 10 f 0.1 f + 2.5v 02404-050 reft refb 0.1 f 0.1 f 0.1 f 10 f + figure 50. resistor-programmable reference (1.5 v p-p input span, differential input with v cm = 2.5 v)
ad9244 rev. c | page 21 of 36 using an external reference to use an external reference, the internal reference must be dis- abled by connecting the sense pin to avdd. the ad9244 contains an internal reference buffer, a2 (see figure 48 ), that simplifies the drive requirements of an external reference. the external reference must be able to drive a 5 k (20%) load. the bandwidth of the reference is deliberately left small to minimize the reference noise contribution. as a result, it is not possible to drive vref externally with high frequencies. figure 51 shows an example of an external reference driving both vinC and vref. in this case, both the common-mode voltage and input span are directly dependent on the value of vref. both the input span and the center of the input span are equal to the external vref. thus, the valid input range extends from (vref + vref/2) to (vref ? vref/2). for example, if the precision reference part ref191 , a 2.048 v external refer- ence, is used, the input span is 2.048 v. in this case, 1 lsb of the ad9244 corresponds to 0.125 mv. it is essential that a minimum of a 10 f capacitor, in parallel with a 0.1 f low inductance ceramic capacitor, decouple the reference output to agnd. 5 v avdd reft refb vref sense ad9244 vin+ vin? 33 20pf 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 10 f 33 + + vref + vref/2 vref ? vref/2 vref 02404-051 figure 51. using an external reference digital outputs table 10 details the relationship among the adc input, otr, and digital output format. data format select (dfs) the ad9244 can be programmed for straight binary or twos complement data on the digital outputs. connect the dfs pin to agnd for straight binary and to avdd for twos complement. digital output driver considerations the ad9244 output drivers can be configured to interface with 5 v or 3.3 v logic families by setting drvdd to 5 v or 3.3 v, respectively. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause glitches on the supplies and can affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts can require external buffers or latches. digital inputs and outputs table 10. output data format input (v) condition (v) binary output mode twos complement mode otr vin+ C vin? < Cvref/2 ? 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 1 vin+ C vin? = ?vref/2 00 0000 0000 0000 10 0000 0000 0000 0 vin+ C vin? = 0 10 0000 0000 0000 00 0000 0000 0000 0 vin+ C vin? = +vref/2 ? 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 0 vin+ C vin? > +vref/2 ? 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 1
ad9244 rev. c | page 22 of 36 out of range (otr) an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. otr is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. thus, otr has the same pipe- line latency as the digital data. otr is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in figure 52 . otr remains high until the analog input returns to within the input range and another conversion is completed. by logically anding otr with the msb and its complement, overrange high or underrange low conditions can be detected. table 11 is a truth table for the overrange/underrange circuit in figure 53 , which uses nand gates. systems requiring programmable gain conditioning of the ad9244 can after eight clock cycles detect an otr condition, thus eliminating gain selection iterations. in addition, otr can be used for digital offset and gain calibration. 1 0 0 0 0 1 otr data outputs otr +fs ? 1 lsb +fs ? 1/2 lsb +fs ?fs ?fs + 1/2 lsb ?fs ? 1/2 lsb 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0000 0000 0000 0000 0001 0000 0000 02404-052 figure 52. otr relation to input voltage and output data table 11. output data format otr msb analog input is 0 0 within range 0 1 within range 1 0 underrange 1 1 overrange msb otr msb over = 1 under = 1 02404-053 figure 53. overrange/underrange logic digital output enable function (oeb) the ad9244 has three-state ability. if the oeb pin is low, the output data drivers are enabled. if the oeb pin is high, the out- put data drivers are placed in a high impedance state. the three-state ability is not intended for rapid access to the data bus. note that oeb is referenced to the digital supplies (drvdd) and should not exceed that supply voltage. clock overview the ad9244 has a flexible clock interface that accepts either a single-ended or differential clock. an internal bias voltage facilitates ac coupling using two external capacitors. to remain backward compatible with the single-pin clock scheme of the ad9226 , the ad9244 can be operated with a dc-coupled, single-pin clock by grounding the clk? pin and driving clk+. when the clk? pin is not grounded, the clk+ and clkC pins function as a differential clock receiver. when clk+ is greater than clkC, the sha is in hold mode; when clk+ is less than clkC, the sha is in track mode (see figure 54 for timing). the rising edge of the clock (clk+ C clkC) switches the sha from track to hold, and timing jitter on this transition should be mini- mized, especially for high frequency analog inputs. clk? clk+ clk? clk+ sha in hold sha in track 02404-054 figure 54. sha timing it is often difficult to maintain a 50% duty cycle to the adc, especially when driving the clock with a single-ended or sine wave input. to ease the constraint of providing an accurate 50% clock, the adc has an optional internal duty cycle stabilizer (dcs) that allows the rising clock edge to pass through with minimal jitter, and interpolates the falling edge, independent of the input clock falling edge. the dcs is described in greater detail in the clock stabilizer (dcs) section.
ad9244 rev. c | page 23 of 36 clock input modes figure 55 to figure 59 illustrate the modes of operation of the clock receiver. figure 55 shows a differential clock directly coupled to clk+ and clkC. in this mode, the common mode of the clk+ and clkC signals should be close to 1.6 v. figure 56 illustrates a single-ended clock input. the capacitor decouples the internal bias voltage on the clkC pin (about 1.6 v), estab- lishing a threshold for the clk+ pin. figure 57 provides backward compatibility with the ad9226 . in this mode, clk? is grounded, and the threshold for clk+ is 1.5 v. figure 58 shows a differential clock ac-coupled by connecting through two capacitors. ac coupling a single-ended clock can also be accomplished using the circuit in figure 59 . when using the differential clock circuits of figure 55 or figure 58 , if clk? drops below 250 mv, the mode of the clock receiver may change, causing conversion errors. it is essential that clk? remains above 250 mv when the clock is ac-coupled or dc-coupled. clock input considerations the analog input is sampled on the rising edge of the clock. timing variations, or jitter, on this edge causes the sampled input voltage to be in error by an amount proportional to the slew rate of the input signal and to the amount of the timing variation. thus, to maintain the excellent high frequency sfdr and snr characteristics of the ad9244, it is essential that the clock edge be kept as clean as possible. the clock should be treated like an analog signal. clock drivers should not share supplies with digital logic or noisy circuits. the clock traces should not run parallel to noisy traces. using a pair of symmetrically routed, differential clock signals can help to provide immunity from common-mode noise coupled from the environment. the clock receiver functions like a differential comparator. at the clk inputs, a slowly changing clock signal results in more jitter than a rapidly changing one. driving the clock with a low amplitude sine wave input is not recommended. running a high speed clock through a divider circuit provides a fast rise/fall time, resulting in the lowest jitter in most systems. clk+ clk? ad9244 02404-055 figure 55. differential clock input, dc-coupled agnd 0.1 f 1.6v clk+ clk? ad9244 02404-056 figure 56. single-ended clock input, dc-coupled agnd clk+ clk? ad9244 02404-057 figure 57. single-ended input, re tains pin compatibility with ad9226 100pf to 0.1 f clk+ clk? ad9244 02404-058 figure 58. differential clock input, ac-coupled 0.1 f agnd 0.1 f 1.6v clk+ clk? ad9244 02404-059 figure 59. single-ended clock input, ac-coupled clock power dissipation most of the power dissipated by the ad9244 is from the analog power supplies. however, lower clock speeds reduce digital supply current. figure 60 shows the relationship between power and clock rate. 02404-060 sample rate (mhz) 70 010 3040 20 50 60 power (mw) 600 550 500 450 400 350 300 250 200 ad9244-40 ad9244-65 figure 60. power consum ption vs. sample rate
ad9244 rev. c | page 24 of 36 clock stabilizer (dcs) the clock stabilizer circuit in the ad9244 desensitizes the adc from clock duty cycle variations. system clock constraints are eased by internally restoring the clock duty cycle to 50%, independent of the clock input duty cycle. low jitter on the rising edge (sampling edge) of the clock is preserved while the falling edge is generated on-chip. it may be desirable to disable the clock stabilizer, or necessary when the clock frequency is varied or completely stopped. note that stopping the clock is not recommended with ac-coupled clocks. once the clock frequency is changed, more than 100 clock cycles may be required for the clock stabilizer to settle to the new speed. when the stabilizer is disabled, the internal switching is directly affected by the clock state. if clk+ is high, the sha is in hold mode; if clk+ is low, the sha is in track mode. figure 25 shows the benefits of using the clock stabilizer. connecting dcs to avdd implements the internal clock stabilization function in the ad9244. if the dcs pin is connected to ground, the ad9244 uses both edges of the external clock in its internal timing circuitry (see the specifications section for timing requirements). grounding and decoupling analog and digital grounding proper grounding is essential in high speed, high resolution systems. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power distribution. the use of power and ground planes offers distinct advantages, including: ? the minimization of the loop area encompassed by a signal and its return path ? the minimization of the impedance associated with ground and power paths ? the inherent distributed capacitor formed by the power plane, pcb material, and ground plane it is important to design a layout that minimizes noise from coupling onto the input signal. digital input signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. while the ad9244 features sepa- rate analog and digital ground pins, it should be treated as an analog component. the agnd and dgnd pins must be joined together directly under the ad9244. a solid ground plane under the adc is acceptable if the power and ground return currents are carefully managed. analog supply decoupling the ad9244 features separate analog and digital supply and ground circuits, helping to minimize digital corruption of sensitive analog signals. in general, avdd (analog power) should be decoupled to agnd (analog ground). the avdd and agnd pins are adjacent to one another. figure 61 shows the recommended decoupling for each pair of analog supplies; 0.1 f ceramic chip and 10 f tantalum capacitors should pro- vide adequately low impedance over a wide frequency range. the decoupling capacitors (especially 0.1 f) should be located as close to the pins as possible. ad9244 avdd agnd 10 f 0.1 f 1 1 locate as close as possible to supply pins. + 02404-061 figure 61. analog supply decoupling digital supply decoupling the digital activity on the ad9244 falls into two categories: correction logic and output drivers. the internal correction logic draws relatively small surges of current, mainly during the clock transitions. the output drivers draw large current impulses when the output bits change state. the size and duration of these currents are a function of the load on the output bits; large capacitive loads should be avoided. for the digital decoupling shown in figure 62 , 0.1 f ceramic chip and 10 f tantalum capacitors are appropriate. the decoupling capacitors (especially 0.1 f) should be located as close to the pins as possible. reasonable capacitive loads on the data pins are less than 20 pf per bit. applications involving greater digital loads should consider increasing the digital decoupling and/or using external buffers/latches. a complete decoupling scheme also includes large tantalum or electrolytic capacitors on the power supply connector to reduce low frequency ripple to insignificant levels. ad9244 drvdd dgnd 10 f 0.1 f 1 1 locate as close as possible to supply pins. + 02404-062 figure 62. digital supply decoupling
ad9244 rev. c | page 25 of 36 reference decoupling the vref pin should be bypassed to the refgnd pin with a 10 f tantalum capacitor in parallel with a low inductance 0.1 f ceramic capacitor. it is also necessary to add a capacitor network to decouple the reft and refb pins. figure 49 shows the recommended decoupling networks. cml the ad9244 has a midsupply reference point. this is used within the internal architecture of the ad9244 and must be decoupled with a 0.1 f capacitor. it sources or sinks a load of up to 300 a. if more current is required, the cml pin should be buffered with an amplifier. vr vr is an internal bias point on the ad9244. it must be decoupled to agnd with a 0.1 f capacitor. ad9244 cml 0.1 f vr 0.1 f 02404-063 figure 63. cml/vr decoupling
ad9244 rev. c | page 26 of 36 evaluation board analog input configuration table 12 provides a summary of the analog input configuration. the analog inputs of the ad9244 on the evaluation board can be driven differentially through a transformer via connector s4, or through the ad8138 amplifier via connector s2, or they can be driven single-ended directly via connector s3. when using the transformer or ad8138 amplifier, a single-ended source can be used, as both of these devices are configured on the ad9244 evaluation board to convert single-ended signals to differential signels. optimal ad9244 performance is achieved above 500 khz by using the input transformer. to drive the ad9244 via the trans- former, connect solderable jumper jp45 and jumper jp46. dc bias is provided by resistor r8 and resistor r28. the evaluation board has positions for through-hole and surface-mount transformers. for applications requiring lower frequencies or dc applications, the ad8138 can be used. the ad8138 provides good distortion and noise performance, as well as input buffering up to 30 mhz. for more information, refer to the ad8138 data sheet. to use the ad8138 to drive the ad9244, remove the transformer (t1 or t4) and connect solderable jumper jp42 and jumper jp43. the ad9244 can be driven single-ended directly via s3 and can be ac-coupled or dc-coupled by removing or inserting jp5. to run the evaluation board in this way, remove the transformer (t1 or t4) and connect solderable jumper jp40 and jumper jp41. resistor r40, resistor r41, resistor r8, and resistor r28 are used to bias the ad9244 inputs to the correct common-mode levels in this application. reference configuration as described in the analog input and reference overview section, the ad9244 can be configured to use its own internal or an external reference. an external reference, d3, and refer- ence buffer, u5, are included on the ad9244 evaluation board. jumper jp8 and jumper jp22 to jumper jp24 can be used to select the desired reference configuration (see table 13 ). clock configuration the ad9244 evaluation board was designed to achieve optimal performance as well as to be easily configurable by the user. to configure the clock input, begin by connecting the correct com- bination of solderable jumpers (see table 14 ). the specific jumper configuration is dependent on the application and can be determined by referring to the clock input modes section. if the differential clock input mode is selected, an external sine wave generator applied to s5 can be used as the clock source. the clock buffer/drive mc10el16 from on semiconductor? is used on the evaluation board to buffer and square the clock input. if the single-ended clock configuration is used, an exter- nal clock source can be applied to s1. the ad9244 evaluation board generates a buffered clock at ttl/cmos levels for use with a data capture system, such as the hsc-adc-eval-sc system. the clock buffering is pro- vided by u4 and u7 and is configured by jumper jp3, jumper jp4, jumper jp9, and jumper jp18 (see table 14 ). table 12. analog input jumper configuration analog input input connector jumpers notes differential: transformer s4 45, 46 r8, r28 provide dc bias; optimal for 500 khz. differential: amplifier s2 42, 43 remove t1 or t4; used for low input frequencies. single-ended s3 5, 40, 41 remove t1 or t4. jp5: conne cted for dc-coupled, not connected for ac-coupling. table 13. reference jumper configuration reference voltage jumpers notes internal 2 v 23 jp8 not connected internal 1 v 24 jp8 not connected internal 1 v vref 2 v 25 jp8 not connected; vref = 1 + r1/r2 external 1 v vref 2 v 8, 22 set vref with r26
ad9244 rev. c | page 27 of 36 table 14. clock jumper configuration clock input input connector jumpers dut clock differential s5 11, 13 single-ended s1 12, 15 ad9226-compatible s1 12, 14 data capture clock internal differential dut clock n/a 9, 18a single-ended dut clock n/a 9, 18b external s6 3 or 4 refin 10mhz refout signal synthesizer 2.5mhz, 0.8v p-p hp8644 clk synthesizer 65mhz, 1v p-p hp8644 2.5mhz band-pass filter avdd gnd dut avdd gnd dut dvdd dvdd ad9244 evaluation board output buss j1 s4 input xfmr s1/s5 input clock dsp equipment clock divider 5v +? 5v +? 3v +? 3v +? 02404-064 figure 64. evaluation board connections
ad9244 rev. c | page 28 of 36 avdd avdd agnd agnd sense vref refgnd refb refb reft reft cml vin+ vin? clk+ clk? agnd agnd avdd avdd dgnd drvdd drvdd dgnd otr msb-d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb-d0 nic oeb vr dfs dcs agnd nic drvdd dgnd otro u1 ad9244 d13o d12o d11o d10o d9o d8o d7o d6o d5o d4o d3o d2o d1o d0o + c56 dnp c57 dnp jp2 jp24 jp25 jp23 jp8 jp22 avdd c2 0.1 f r6 1k c40 0.001 f c45 0.001 f c1 10 f 10v dutdrvdd c50 0.1 f jp12 seclk r4 dnp r3 dnp wht tp5 vin+ vin? 1 2 d3 cw a vdd r16 2.55k c29 0.1 f +in ?in out r20 2k c28 0.1 f c27 10 f 10v 22 23 29 30 34 31 33 32 6 7 47 46 45 42 41 40 39 38 37 36 2 1 4 3 14 15 44 5 43 35 48 9 8 10 11 12 13 16 17 18 19 20 21 24 25 26 27 28 jp6 jp1 r42 1k r10 1k c37 0.1 f + c41 0.001 f c42 0.001 f c23 10 f 10v dutavdd c38 0.1 f + c39 0.001 f c22 10 f 10v dutavdd c36 0.1 f + c35 0.1 f c21 10 f 10v + + jp11 diffa jp14 jp13 diffb jp15 c30 0.1 f c33 0.1 f c20 10 f 10v + c32 0.1 f c34 0.1 f 2 3 1 7 agnd; 4 avdd; 8 r17 2k r26 2k u5 ad822 +in ?in out 6 5 agnd; 4 avdd; 8 u5 ad822 avdd fbead l1 tp2 red dutavdd c59 0.1 f c58 22 f 25v dutavddin + 2 tb1 agnd 3 tb1 fbead l2 tp1 red avdd c52 0.1 f c47 22 f 25v avddin + 1 tb1 fbead l3 tp3 red dutdrvdd c53 0.1 f c48 22 f 25v drvddin + 5 tb1 agnd 4 tb1 fbead l4 tp4 red dvdd c14 0.1 f c6 22 f 25v dvddin + 6 tb1 tp11 blk tp12 blk tp13 blk tp14 blk 02404-065 1.2v figure 65. ad9244 evaluation board, adc, ex ternal reference, and power supply circuitry
ad9244 rev. c | page 29 of 36 vcc q q vee reset clk clk vbb u3 mc10el16 1 2 3 4 8 7 6 5 avdd diffa diffb avdd cw avdd diffclk s5 18 1 16 y1 y2 y3 y4 y5 y6 y7 y8 17 2 15 16 3 14 15 4 13 14 5 12 13 6 11 12 7 10 11 8 9 a1 a2 y3 a4 a5 a6 a7 a8 2 3 4 5 6 7 8 9 u6 74vhc541 19 1 g2 g1 10 20 gnd vcc dvdd header right angle male no ejectors j1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 msb clk otr d13 d12 d11 d10 d9 d8 d7 d6 18 otro otr d0o d0 avdd u3 decoupling u4 9 8 74vhc04 u4 11 10 74vhc04 74vhc04 jp9 jp3 jp4 seclk tp7 wht jp18 ab 1 3 2 s6 dataclk avdd r27 2k cw 27 d13o d13 36 d12o d12 45 d11o d11 18 d10o d10 27 d9o d9 36 d8o d8 45 d7o d7 18 d6o d6 27 d5o d5 36 d4o d4 45 18 d3o d3 27 d2o d2 36 d1o d1 45 + 18 y1 y2 y3 y4 y5 y6 y7 y8 17 16 15 14 13 12 11 a1 a2 y3 a4 a5 a6 a7 a8 2 3 4 5 6 7 8 9 u7 74vhc541 19 1 g2 g1 10 20 gnd vcc d5 d4 d3 d2 d1 d0 otr + 11 6 21 5 31 4 41 3 51 2 61 1 71 0 89 u4 1 2 cw avdd avdd seclk s1 74vhc04 u4 5 6 74vhc04 u4 3 4 74vhc04 u4 13 12 02404-066 avdd; 14 agnd; 7 + + u4 decoupling avdd figure 66. ad9244 evaluation board, clock input, and digital output buffer circuitry
ad9244 rev. c | page 30 of 36 c69 0.1 f c15 10 f 10v avdd s2 r31 49.9 ?in +in v? v+ out? out+ u2 ad8138 v ocm 1 8 6 5 3 4 2 r36 499 r35 499 amp input r34 523 r37 499 c8 0.1 f r32 10k r33 10k avdd r46 33 r47 33 jp42 r21 33 c44 dnp vin+ vin? r22 33 c43 dnp c7 0.1 f r41 1k r40 1k a v dd c9 0.33 f jp5 r5 49.9 single input s3 nc= 2 ps adt4-6t t4 t1 ps t1-1tx65 16 5 34 nc = 5 1 2 3 5 4 r24 49.9 s4 xfmrinput c24 20pf r8 500 c25 0.33 f c16 0.1 f avdd cw r28 2k + jp45 jp40 jp46 jp43 jp41 02404-067 figure 67. ad9244 evaluation board, analog input circuitry
ad9244 rev. c | page 31 of 36 02404-068 figure 68. ad9244 evaluation board, pcb assembly, top 02404-069 figure 69. ad9244 evaluation board, pcb assembly, bottom
ad9244 rev. c | page 32 of 36 02404-070 figure 70. ad9244 evaluation board, pcb layer 1 (top) 02404-071 figure 71. ad9244 evaluation board, pcb layer 2 (ground plane)
ad9244 rev. c | page 33 of 36 02404-072 figure 72. ad9244 evaluation board, pcb layer 3 (power plane) 02404-073 figure 73. ad9244 evaluation board, pcb layer 4 (bottom)
ad9244 rev. c | page 34 of 36 table 15. evaluation board bill of materials item qty. reference designator description package value 1 11 c1, c3, c4, c5, c15, c20, c21, c22, c23, c26, c27 tantalum capacitors bcase 10 f 2 28 c2, c7, c8, c10, c11, c12, c13, c14, c16, c17, c18, c19, c28, c29, c31, c32, c33, c34, c35, c36, c37, c38, c50, c52, c53, c59, c61, c69 chip capacitors 1206 0.1 f 3 4 c6, c47, c48, c58 tantalum capacitors dcase 22 f 4 2 c9, c25 chip capacitors 1206 0.33 f 5 1 c24 chip capacitor 0805 20 pf 6 3 c30, c46, c49 chip capacitors 0805 0.1 f 7 5 c39, c40, c41, c42, c45 chip capacitors 0805 0.001 f 8 2 c43, c44 dnp 1 0805 dnp 1 9 1 c60 chip capacitor 1206 0.01 f 10 1 d3 diode sot-23 can 1.2 v 11 1 j1 header male 40 pin ra header 12 12 jp1, jp2, jp3, jp4, jp5, jp6, jp8, jp9, jp22, jp23, jp24, jp25 headers jprblk02 13 11 jp11, jp12, jp13, jp14, jp15, jp40, jp41, jp42, jp43, jp45, jp46 solder jumpers 14 1 jp18 header jprblk03 15 4 l1, l2, l3, l4 chip inductors lc1210 fbead 16 6 r1, r5, r11, r24, r29, r31 chip resistors rc07cup 49.9 17 1 r2 potentiometer rv3299up 5 k 18 2 r3, r4 dnp 1 rc07cup dnp 1 19 5 r6, r10, r40, r41, r42 chip resistors 1206 1 k 20 2 r7, r9 chip resistors 1206 22 21 1 r8 chip resistor 1206 500 22 2 r12, r13 chip resistors 1206 113 23 2 r14, r15 chip resistors 1206 90 24 1 r16 chip resistor 1206 2.55 k 25 2 r17, r20 chip resistors 1206 2 k 26 2 r18, r19 chip resistors 1206 4 k 27 6 r21, r22, r23, r25, r46, r47 chip resistors 1206 33 28 3 r26, r27, r28 potentiometers rv3299up 2 k 29 4 r30, r32, r33, r38 chip resistors 1206 10 k 30 1 r34 chip resistor 1206 523 31 3 r35, r36, r37 chip resistors 1206 499 32 1 r39 chip resistor 1206 49.9 33 2 r43, r44 chip resistors 1206 100 34 1 r45 potentiometer rv3299up 10 k 35 2 rp1, rp2 resistor packs rcts766 22 36 4 rp3, rp4, rp5, rp6 resistor packs rca74204 22 37 6 s1, s2, s3, s4, s5, s6 sma connectors 50 sma200up 38 1 t1 transformer dip06rcup t1-1tx65 39 1 t4 transformer mini_cd637 adt4-6t 40 1 tb1 header tblk06rem 40a 1 tb1a header 41 4 tp1, tp2, tp3, tp4 test points looptp red 42 2 tp5, tp7 test points loopmini wht 43 4 tp11, tp12, tp13, tp14 test points looptp blk 44 1 u1 ad9244 lqfp-48 ad9244 45 1 u2 ad8138 amplifier r-8 ad8138 46 1 u3 ecl divider so8 mc10el16 47 1 u4 hex inverter tssop14 74vhc04mtc 48 1 u5 ad822 op amp soic-8 ad822 49 2 u6, u7 octal registers sol20 74vhc541
ad9244 rev. c | page 35 of 36 item qty. reference designator description package value 50 14 sockets for through resistors solder sockets 51 2 c56, c57 dnp 1 total 183 1 do not place.
ad9244 rev. c | page 36 of 36 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 74. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model temperature range package description package option ad9244bst-65 C40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad9244bstrl-65 C40c to +85c 48-lead low pr ofile quad flat package (lqfp) st-48 ad9244bstz-65 1 C40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad9244bstzrl-65 1 C40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad9244bst-40 C40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad9244bstrl-40 C40c to +85c 48-lead low pr ofile quad flat package (lqfp) st-48 ad9244bstz-40 1 C40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad9244bstzrl-40 1 C40c to +85c 48-lead low profile quad flat package (lqfp) st-48 AD9244-65PCB evaluation board ad9244-40pcb evaluation board 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02404-0-12/05(c)

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